1. Field of the Invention
The present invention relates generally to bus bridges, and specifically, to a method and apparatus for decoupling internal latencies of a bus bridge from those on an external bus.
2. Background Information
In a typical computer system, a central processing unit or microprocessor, on a host bus, is coupled to system memory and one or more devices on a secondary bus by way of a bus bridge. The bus bridge bridges transactions between the microprocessor, one or more devices on the secondary bus, and the system memory. The bus bridge also decouples the microprocessor from activities between the system memory and the secondary bus. When the microprocessor attempts a write cycle to, for example, system memory, it waits for the assertion of target ready (TRDY#) by the bus bridge before initiating the transfer of data on the host bus. The P6 Bus Protocol, Revision 4, published in August 1995 by Intel.RTM. Corporation of Santa Clara, Calif., allows for the assertion of TRDY#, at the earliest, four clock cycles from the beginning of the cycle. When the bus bridge is the target of a microprocessor initiated write cycle, it has to take the following actions before it can assert TRDY# on the host bus: (i) Decode the cycle and determine its destination; (ii) assert a request to the destination unit and wait for a response back from that destination unit; and (iii) if the destination unit is capable of accepting the data, assert TRDY# on the host bus. At 100 Mhz, for example, the response from the destination unit can be received, at the earliest, in T4. This pushes out the assertion of TRDY# to T5 and, subsequently, the data transfer is pushed out by a clock relative to the earliest possible transfer point. It would be desirable to minimize the amount of latency involved in such a cycle.